# 1 "FWlib/apt32f102_syscon.c"
# 1 "E:\\APT_Landscape_mode\\APT32F1023_New\\Source//"
# 1 "<built-in>"
# 1 "<command-line>"
# 1 "FWlib/apt32f102_syscon.c"
# 19 "FWlib/apt32f102_syscon.c"
# 1 "include/apt32f102_syscon.h" 1
# 23 "include/apt32f102_syscon.h"
# 1 "include/apt32f102.h" 1
# 23 "include/apt32f102.h"
# 1 "include/apt32f102_types_local.h" 1
# 63 "include/apt32f102_types_local.h"
typedef signed char S8_T;
typedef short S16_T;
typedef long S32_T;


typedef unsigned char U8_T;
typedef unsigned short U16_T;
typedef unsigned long U32_T;
typedef unsigned long long U64_T;


typedef float F32_T;
typedef double F64_T;


typedef U8_T B_T;
# 100 "include/apt32f102_types_local.h"
typedef enum {ENABLE = 1, DISABLE = !ENABLE} ClockStatus, FunctionalStatus;
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;




typedef volatile U32_T CSP_REGISTER_T;
typedef volatile U16_T CSP_REGISTER16_T;
typedef volatile U8_T CSP_REGISTER8_T;




typedef unsigned char UINT8;
typedef signed char SINT8;


typedef unsigned short UINT16;
typedef signed short SINT16;


typedef unsigned long UINT32;
typedef signed long SINT32;

typedef void VOID;
typedef signed char CHAR;
typedef unsigned char BOOL;
typedef signed long TIME_T;

typedef float SINGLE;



typedef double DOUBLE;

typedef struct
{
  unsigned bit0 : 1;
  unsigned bit1 : 1;
  unsigned bit2 : 1;
  unsigned bit3 : 1;
  unsigned bit4 : 1;
  unsigned bit5 : 1;
  unsigned bit6 : 1;
  unsigned bit7 : 1;
} REG8;

typedef struct
{
  unsigned bit0 : 1;
  unsigned bit1 : 1;
  unsigned bit2 : 1;
  unsigned bit3 : 1;
  unsigned bit4 : 1;
  unsigned bit5 : 1;
  unsigned bit6 : 1;
  unsigned bit7 : 1;
  unsigned bit8 : 1;
  unsigned bit9 : 1;
  unsigned bit10: 1;
  unsigned bit11: 1;
  unsigned bit12: 1;
  unsigned bit13: 1;
  unsigned bit14: 1;
  unsigned bit15: 1;
} REG16;






typedef char STRING_3[4];
typedef char STRING_5[6];
typedef char STRING_8[9];
typedef char STRING_10[11];
typedef char STRING_12[13];
typedef char STRING_16[17];
typedef char STRING_24[25];
typedef char STRING_30[31];
typedef char STRING_32[33];
typedef char STRING_48[49];
typedef char STRING_50[51];
typedef char STRING_60[61];
typedef char STRING_80[81];
typedef char STRING_132[133];
typedef char STRING_256[257];
typedef char STRING_512[513];
# 24 "include/apt32f102.h" 2
# 1 "include/apt32f102_ck801.h" 1
# 85 "include/apt32f102_ck801.h"
typedef enum IRQn
{

        ISR_Restart = -32,
        ISR_Misaligned_Access = -31,
        ISR_Access_Error = -30,
        ISR_Divided_By_Zero = -29,
        ISR_Illegal = -28,
        ISR_Privlege_Violation = -27,
        ISR_Trace_Exection = -26,
        ISR_Breakpoint_Exception = -25,
        ISR_Unrecoverable_Error = -24,
        ISR_Idly4_Error = -23,
        ISR_Auto_INT = -22,
        ISR_Auto_FINT = -21,
        ISR_Reserved_HAI = -20,
        ISR_Reserved_FP = -19,
        ISR_TLB_Ins_Empty = -18,
        ISR_TLB_Data_Empty = -17,

        INTC_CORETIM_IRQn = 0,
        INTC_TIME1_IRQn = 1,
        INTC_UART0_IRQn = 2,
        INTC_GPIOA2_IRQn = 8,
} IRQn_Type;


void INTC_Init(void);
void force_interrupt(IRQn_Type IRQn);

void CK_CPU_EnAllNormalIrq(void);
void CK_CPU_DisAllNormalIrq(void);
# 25 "include/apt32f102.h" 2




typedef struct {
 volatile unsigned int ReservedA[4];
 volatile unsigned int CORET_CSR;
 volatile unsigned int CORET_RVR;
 volatile unsigned int CORET_CVR;
 volatile unsigned int CORET_CALIB;
 volatile unsigned int ReservedB[56];
 volatile unsigned int ISER;
 volatile unsigned int ReservedC[15];
 volatile unsigned int IWER;
 volatile unsigned int ReservedD[15];
 volatile unsigned int ICER;
 volatile unsigned int ReservedE[15];
 volatile unsigned int IWDR;
 volatile unsigned int ReservedF[15];
 volatile unsigned int ISPR;
 volatile unsigned int ReservedG[31];
 volatile unsigned int ICPR;
 volatile unsigned int ReservedH[31];
 volatile unsigned int IABR;
 volatile unsigned int ReservedI[63];
 volatile unsigned int IPR[8];
 volatile unsigned int ReservedJ[504];
 volatile unsigned int ISR;
 volatile unsigned int IPTR;
} CSP_CK801_T;



typedef volatile struct {
 volatile unsigned int IDR ;
 volatile unsigned int CEDR ;
 volatile unsigned int SRR ;
 volatile unsigned int CMR ;
 volatile unsigned int CR ;
 volatile unsigned int MR ;
 volatile unsigned int FM_ADDR ;
 volatile unsigned int Reserved ;
 volatile unsigned int KR ;
 volatile unsigned int IMCR ;
 volatile unsigned int RISR ;
 volatile unsigned int MISR ;
 volatile unsigned int ICR ;
} CSP_IFC_T ;



typedef volatile struct {
 volatile unsigned int IDCCR;
 volatile unsigned int GCER;
 volatile unsigned int GCDR;
 volatile unsigned int GCSR;
 volatile unsigned int CKST;
 volatile unsigned int RAMCHK;
 volatile unsigned int EFLCHK;
 volatile unsigned int SCLKCR;
 volatile unsigned int PCLKCR;
 volatile unsigned int _RSVD0;
 volatile unsigned int PCER0;
 volatile unsigned int PCDR0;
 volatile unsigned int PCSR0;
 volatile unsigned int PCER1;
 volatile unsigned int PCDR1;
 volatile unsigned int PCSR1;
 volatile unsigned int OSTR;
 volatile unsigned int _RSVD1;
 volatile unsigned int _RSVD2;
 volatile unsigned int LVDCR;
 volatile unsigned int CLCR;
 volatile unsigned int PWRCR;
 volatile unsigned int PWRKEY;
 volatile unsigned int _RSVD3;
 volatile unsigned int _RSVD4;
 volatile unsigned int OPT1;
 volatile unsigned int OPT0;
 volatile unsigned int WKCR;
 volatile unsigned int _RSVD5;
 volatile unsigned int IMER;
 volatile unsigned int IMDR;
 volatile unsigned int IMCR;
 volatile unsigned int IAR;
 volatile unsigned int ICR;
 volatile unsigned int RISR;
 volatile unsigned int MISR;
 volatile unsigned int RSR;
 volatile unsigned int EXIRT;
 volatile unsigned int EXIFT;
 volatile unsigned int EXIER;
 volatile unsigned int EXIDR;
 volatile unsigned int EXIMR;
 volatile unsigned int EXIAR;
 volatile unsigned int EXICR;
 volatile unsigned int EXIRS;
 volatile unsigned int IWDCR;
 volatile unsigned int IWDCNT;
 volatile unsigned int IWDEDR;
 volatile unsigned int IOMAP0;
 volatile unsigned int IOMAP1;
 volatile unsigned int CINF0;
 volatile unsigned int CINF1;
 volatile unsigned int FINF0;
 volatile unsigned int FINF1;
 volatile unsigned int FINF2;
 volatile unsigned int _RSVD6;
 volatile unsigned int ERRINF;
 volatile unsigned int UID0 ;
 volatile unsigned int UID1 ;
 volatile unsigned int UID2 ;
 volatile unsigned int PWROPT;
 volatile unsigned int EVTRG;
 volatile unsigned int EVPS;
 volatile unsigned int EVSWF;
 volatile unsigned int UREG0;
 volatile unsigned int UREG1;
 volatile unsigned int UREG2;
 volatile unsigned int UREG3;
} CSP_SYSCON_T;



 typedef volatile struct
 {
    volatile unsigned int EN;
    volatile unsigned int SWTRG;
    volatile unsigned int CH0CON0;
    volatile unsigned int CH0CON1;
    volatile unsigned int CH1CON0;
    volatile unsigned int CH1CON1;
    volatile unsigned int CH2CON0;
    volatile unsigned int CH2CON1;
 volatile unsigned int _RSVD0;
 volatile unsigned int _RSVD1;
 volatile unsigned int _RSVD2;
 volatile unsigned int _RSVD3;
    volatile unsigned int CH3CON;
 volatile unsigned int CH4CON;
 volatile unsigned int CH5CON;
 volatile unsigned int CH6CON;
 volatile unsigned int CH7CON;
 } CSP_ETCB_T, *CSP_ETCB_PTR;



typedef volatile struct
{
   volatile unsigned int TCH_CCR;
   volatile unsigned int TCH_CON0;
   volatile unsigned int TCH_CON1;
   volatile unsigned int TCH_SCCR;
   volatile unsigned int TCH_SENPRD;
   volatile unsigned int TCH_VALBUF;
   volatile unsigned int TCH_SENCNT;
   volatile unsigned int TCH_TCHCNT;
   volatile unsigned int TCH_THR;
   volatile unsigned int Reserved0;
   volatile unsigned int TCH_RISR;
   volatile unsigned int TCH_IER;
   volatile unsigned int TCH_ICR;
   volatile unsigned int TCH_RWSR;
   volatile unsigned int TCH_OVW_THR;
   volatile unsigned int TCH_OVF;
   volatile unsigned int TCH_OVT;
   volatile unsigned int TCH_SYNCR;
   volatile unsigned int TCH_EVTRG;
   volatile unsigned int TCH_EVPS;
   volatile unsigned int TCH_EVSWF;
} CSP_TKEY_T, *CSP_TKEY_PTR;



typedef volatile struct
{
   volatile unsigned int TCH_CHVAL[18];
   volatile unsigned int TCH_SEQCON[18];
} CSP_TKEYBUF_T, *CSP_TKEYBUF_PTR;



 typedef volatile struct
 {
    volatile unsigned int ECR;
    volatile unsigned int DCR;
    volatile unsigned int PMSR;
    volatile unsigned int Reserved0;
    volatile unsigned int CR;
    volatile unsigned int MR;
    volatile unsigned int SHR;
    volatile unsigned int CSR;
    volatile unsigned int SR;
    volatile unsigned int IER;
    volatile unsigned int IDR;
    volatile unsigned int IMR;
    volatile unsigned int SEQ[16];
    volatile unsigned int PRI;
    volatile unsigned int TDL0;
    volatile unsigned int TDL1;
    volatile unsigned int SYNCR;
    volatile unsigned int Reserved1;
    volatile unsigned int Reserved2;
    volatile unsigned int EVTRG;
    volatile unsigned int EVPS;
    volatile unsigned int EVSWF;
    volatile unsigned int ReservedD[27];
    volatile unsigned int DR[16];
    volatile unsigned int CMP0;
    volatile unsigned int CMP1;
 volatile unsigned int DRMASK;
 } CSP_ADC12_T, *CSP_ADC12_PTR;



 typedef volatile struct
 {
    volatile unsigned int CONLR;
    volatile unsigned int CONHR;
    volatile unsigned int WODR;
    volatile unsigned int SODR;
    volatile unsigned int CODR;
    volatile unsigned int ODSR;
    volatile unsigned int PSDR;
    volatile unsigned int FLTEN;
    volatile unsigned int PUDR;
    volatile unsigned int DSCR;
    volatile unsigned int OMCR;
    volatile unsigned int IECR;
 volatile unsigned int IEER;
 volatile unsigned int IEDR;
 } CSP_GPIO_T, *CSP_GPIO_PTR;

 typedef volatile struct
 {
 volatile unsigned int IGRPL;
    volatile unsigned int IGRPH;
 volatile unsigned int IGREX;
    volatile unsigned int IO_CLKEN;
 } CSP_IGRP_T, *CSP_IGRP_PTR;



 typedef volatile struct
 {
    volatile unsigned int DATA;
    volatile unsigned int SR;
    volatile unsigned int CTRL;
    volatile unsigned int ISR;
    volatile unsigned int BRDIV;
    volatile unsigned int ReservedA[20];
 } CSP_UART_T, *CSP_UART_PTR;



typedef struct
{
 volatile unsigned int CR0;
 volatile unsigned int CR1;
 volatile unsigned int DR;
 volatile unsigned int SR;
 volatile unsigned int CPSR;
 volatile unsigned int IMSCR;
 volatile unsigned int RISR;
 volatile unsigned int MISR;
 volatile unsigned int ICR;
} CSP_SSP_T, *CSP_SSP_PTR;



typedef struct
{
 volatile unsigned int CR;
 volatile unsigned int TXCR0;
 volatile unsigned int TXCR1;
 volatile unsigned int TXBUF;
 volatile unsigned int RXCR0;
 volatile unsigned int RXCR1;
 volatile unsigned int RXCR2;
 volatile unsigned int RXBUF;
 volatile unsigned int RISR;
 volatile unsigned int MISR;
 volatile unsigned int IMCR;
 volatile unsigned int ICR;
} CSP_SIO_T, *CSP_SIO_PTR;



 typedef volatile struct
 {
    unsigned int CR;
    unsigned int TADDR;
    unsigned int SADDR;
    unsigned int ReservedD;
    unsigned int DATA_CMD;
    unsigned int SS_SCLH;
    unsigned int SS_SCLL;
    unsigned int FS_SCLH;
    unsigned int FS_SCLL;
    unsigned int ReservedA;
    unsigned int ReservedC;
    unsigned int RX_FLSEL;
    unsigned int TX_FLSEL;
    unsigned int RX_FL;
    unsigned int TX_FL;
    unsigned int ENABLE;
    unsigned int STATUS;
    unsigned int ReservedB;
    unsigned int SDA_TSETUP;
    unsigned int SDA_THOLD;
    unsigned int SPKLEN;

    unsigned int ReservedE;
 unsigned int MISR;
    unsigned int IMSCR;
    unsigned int RISR;
    unsigned int ICR;
    unsigned int ReservedF;
    unsigned int SCL_TOUT;
    unsigned int SDA_TOUT;
    unsigned int TX_ABRT;
    unsigned int GCALL;
    unsigned int NACK;
 } CSP_I2C_T, *CSP_I2C_PTR;



 typedef struct
 {
    volatile unsigned int CADATAH;
    volatile unsigned int CADATAL;
    volatile unsigned int CACON;
    volatile unsigned int INTMASK;
 } CSP_CA_T, *CSP_CA_PTR;



 typedef struct
 {
 volatile unsigned int CEDR;
 volatile unsigned int RSSR;
 volatile unsigned int PSCR;
 volatile unsigned int CR;
 volatile unsigned int SYNCR;
 volatile unsigned int GLDCR;
 volatile unsigned int GLDCFG;
 volatile unsigned int GLDCR2;
 volatile unsigned int Reserved0;
 volatile unsigned int PRDR;
 volatile unsigned int Reserved1;
 volatile unsigned int CMPA;
 volatile unsigned int CMPB;
 volatile unsigned int Reserved2;
 volatile unsigned int Reserved3;
 volatile unsigned int CMPLDR;
 volatile unsigned int CNT;
 volatile unsigned int AQLDR;
 volatile unsigned int AQCRA;
 volatile unsigned int AQCRB;
 volatile unsigned int Reserved4;
 volatile unsigned int Reserved5;
 volatile unsigned int Reserved6;
 volatile unsigned int AQOSF;
 volatile unsigned int AQCSF;
 volatile unsigned int Reserved7;
 volatile unsigned int Reserved8;
 volatile unsigned int Reserved9;
 volatile unsigned int Reserved10;
 volatile unsigned int Reserved11;
 volatile unsigned int Reserved12;
 volatile unsigned int Reserved13;
 volatile unsigned int Reserved14;
 volatile unsigned int Reserved15;
 volatile unsigned int Reserved16;
 volatile unsigned int Reserved17;
 volatile unsigned int Reserved18;
 volatile unsigned int Reserved19;
 volatile unsigned int Reserved20;
 volatile unsigned int Reserved21;
 volatile unsigned int Reserved22;
 volatile unsigned int Reserved23;
 volatile unsigned int Reserved24;
 volatile unsigned int Reserved25;
 volatile unsigned int Reserved26;
 volatile unsigned int Reserved27;
 volatile unsigned int TRGFTCR;
 volatile unsigned int TRGFTWR;
 volatile unsigned int EVTRG;
 volatile unsigned int EVPS;
 volatile unsigned int EVCNTINIT;
 volatile unsigned int EVSWF;
 volatile unsigned int RISR;
 volatile unsigned int MISR;
 volatile unsigned int IMCR;
 volatile unsigned int ICR;
 volatile unsigned int REGLINK;

 }CSP_GPT_T,*CSP_GPT_PTR;



 typedef struct
 {
   volatile unsigned int CEDR;
   volatile unsigned int RSSR;
   volatile unsigned int PSCR;
   volatile unsigned int CR;
   volatile unsigned int SYNCR;
   volatile unsigned int GLDCR;
   volatile unsigned int GLDCFG;
   volatile unsigned int GLDCR2;
   volatile unsigned int HRCFG;
   volatile unsigned int PRDR;
   volatile unsigned int PHSR;
   volatile unsigned int CMPA;
   volatile unsigned int CMPB;
   volatile unsigned int CMPC;
   volatile unsigned int CMPD;
   volatile unsigned int CMPLDR;
   volatile unsigned int CNT;
   volatile unsigned int AQLDR;
   volatile unsigned int AQCRA;
   volatile unsigned int AQCRB;
   volatile unsigned int AQCRC;
   volatile unsigned int AQCRD;
   volatile unsigned int AQTSCR;
   volatile unsigned int AQOSF;
   volatile unsigned int AQCSF;
   volatile unsigned int DBLDR;
   volatile unsigned int DBCR;
   volatile unsigned int DPSCR;
   volatile unsigned int DBDTR;
   volatile unsigned int DBDTF;
   volatile unsigned int CPCR;
   volatile unsigned int EMSRC;
   volatile unsigned int EMSRC2;
   volatile unsigned int EMPOL;
   volatile unsigned int EMECR;
   volatile unsigned int EMOSR;
   volatile unsigned int Reserved;
   volatile unsigned int EMSLSR;
   volatile unsigned int EMSLCLR;
   volatile unsigned int EMHLSR;
   volatile unsigned int EMHLCLR;
   volatile unsigned int EMFRCR;
   volatile unsigned int EMRISR;
   volatile unsigned int EMMISR;
   volatile unsigned int EMIMCR;
   volatile unsigned int EMICR;
   volatile unsigned int TRGFTCR;
   volatile unsigned int TRGFTWR;
   volatile unsigned int EVTRG;
   volatile unsigned int EVPS;
   volatile unsigned int EVCNTINIT;
   volatile unsigned int EVSWF;
   volatile unsigned int RISR;
   volatile unsigned int MISR;
   volatile unsigned int IMCR;
   volatile unsigned int ICR;
   volatile unsigned int REGLINK;
   volatile unsigned int REGLINK2;
   volatile unsigned int REGPROT;
} CSP_EPT_T, *CSP_EPT_PTR;



 typedef volatile struct
 {
   volatile unsigned int CEDR;
   volatile unsigned int RSSR;
   volatile unsigned int PSCR;
   volatile unsigned int CR;
   volatile unsigned int SYNCR;
   volatile unsigned int PRDR;
   volatile unsigned int CMP;
   volatile unsigned int CNT;
   volatile unsigned int TRGFTCR;
   volatile unsigned int TRGFTWR;
   volatile unsigned int EVTRG;
   volatile unsigned int EVPS;
   volatile unsigned int EVSWF;
   volatile unsigned int RISR;
   volatile unsigned int MISR;
   volatile unsigned int IMCR;
   volatile unsigned int ICR;
} CSP_LPT_T, *CSP_LPT_PTR;



 typedef struct
 {
   volatile unsigned int RSSR;
   volatile unsigned int CR;
   volatile unsigned int PSCR;
   volatile unsigned int PRDR;
   volatile unsigned int CMP;
   volatile unsigned int CNT;
   volatile unsigned int EVTRG;
   volatile unsigned int EVPS;
   volatile unsigned int EVCNTINTI;
   volatile unsigned int EVSWF;
   volatile unsigned int RISR;
   volatile unsigned int IMCR;
   volatile unsigned int MISR;
   volatile unsigned int ICR;
} CSP_BT_T, *CSP_BT_PTR;



typedef struct
{
   volatile unsigned int IDR;
   volatile unsigned int CEDR;
   volatile unsigned int SRR;
   volatile unsigned int CR;
   volatile unsigned int SEED;
   volatile unsigned int DATAIN;
   volatile unsigned int DATAOUT;

} CSP_CRC_T, *CSP_CRC_PTR;



 typedef struct
 {
   volatile unsigned int TIMR;
   volatile unsigned int DATR;
   volatile unsigned int CR;
   volatile unsigned int CCR;
   volatile unsigned int ALRAR;
   volatile unsigned int ALRBR;
   volatile unsigned int SSR;
   volatile unsigned int CAL;
   volatile unsigned int RISR;
   volatile unsigned int IMCR;
   volatile unsigned int MISR;
   volatile unsigned int ICR;
   volatile unsigned int KEY;
   volatile unsigned int EVTRG;
   volatile unsigned int EVPS;
   volatile unsigned int EVSWF;
} CSP_RTC_T, *CSP_RTC_PTR;




 typedef struct
 {
  volatile unsigned int CR;
  volatile unsigned int CFGR;
  volatile unsigned int RISR;
  volatile unsigned int MISR;
  volatile unsigned int IMCR;
  volatile unsigned int ICR;
 }CSP_WWDT_T,*CSP_WWDT_PTR;



 typedef struct
 {
  volatile S32_T DIVIDENT;
  volatile S32_T DIVISOR;
  volatile S32_T QUOTIENT;
  volatile S32_T REMAIN;
  volatile unsigned int CR;
 }CSP_HWD_T,*CSP_HWD_PTR;
# 691 "include/apt32f102.h"
extern CSP_CK801_T *CK801 ;

extern CSP_IFC_T *IFC ;
extern CSP_SYSCON_T *SYSCON ;
extern CSP_ETCB_T *ETCB ;

extern CSP_TKEY_T *TKEY ;
extern CSP_TKEYBUF_T *TKEYBUF ;
extern CSP_ADC12_T *ADC0 ;

extern CSP_GPIO_T *GPIOA0 ;
extern CSP_GPIO_T *GPIOB0 ;
extern CSP_IGRP_T *GPIOGRP ;

extern CSP_UART_T *UART0 ;
extern CSP_UART_T *UART1 ;
extern CSP_UART_T *UART2 ;
extern CSP_SSP_T *SPI0 ;
extern CSP_SIO_T *SIO0 ;
extern CSP_I2C_T *I2C0 ;
extern CSP_CA_T *CA0 ;

extern CSP_GPT_T *GPT0 ;

extern CSP_EPT_T *EPT0 ;

extern CSP_LPT_T *LPT ;
extern CSP_HWD_T *HWD ;
extern CSP_WWDT_T *WWDT ;
extern CSP_BT_T *BT0 ;
extern CSP_BT_T *BT1 ;

extern CSP_CRC_T *CRC ;
extern CSP_RTC_T *RTC ;


void MisalignedHandler(void) __attribute__((isr));
void IllegalInstrHandler(void) __attribute__((isr));
void AccessErrHandler(void) __attribute__((isr));
void BreakPointHandler(void) __attribute__((isr));
void UnrecExecpHandler(void) __attribute__((isr));
void Trap0Handler(void) __attribute__((isr));
void Trap1Handler(void) __attribute__((isr));
void Trap2Handler(void) __attribute__((isr));
void Trap3Handler(void) __attribute__((isr));
void PendTrapHandler(void) __attribute__((isr));

void CORETHandler(void) __attribute__((isr));
void SYSCONIntHandler(void) __attribute__((isr));
void IFCIntHandler(void) __attribute__((isr));
void ADCIntHandler(void) __attribute__((isr));
void EPT0IntHandler(void) __attribute__((isr));
void WWDTHandler(void) __attribute__((isr));
void EXI0IntHandler(void) __attribute__((isr));
void EXI1IntHandler(void) __attribute__((isr));
void EXI2to3IntHandler(void) __attribute__((isr));
void EXI4to9IntHandler(void) __attribute__((isr));
void EXI10to15IntHandler(void) __attribute__((isr));
void UART0IntHandler(void) __attribute__((isr));
void UART1IntHandler(void) __attribute__((isr));
void UART2IntHandler(void) __attribute__((isr));
void I2CIntHandler(void) __attribute__((isr));
void GPT0IntHandler(void) __attribute__((isr));
void LEDIntHandler(void) __attribute__((isr));
void TKEYIntHandler(void) __attribute__((isr));
void SPI0IntHandler(void) __attribute__((isr));
void SIO0IntHandler(void) __attribute__((isr));
void CNTAIntHandler(void) __attribute__((isr));
void RTCIntHandler(void) __attribute__((isr));
void LPTIntHandler(void) __attribute__((isr));
void BT0IntHandler(void) __attribute__((isr));
void BT1IntHandler(void) __attribute__((isr));

extern int __divsi3 (int a, int b);
extern unsigned int __udivsi3 (unsigned int a, unsigned int b);
extern int __modsi3 (int a, int b);
extern unsigned int __umodsi3 (unsigned int a, unsigned int b);
extern void delay_nms(unsigned int t);
extern void delay_nus(unsigned int t);
# 24 "include/apt32f102_syscon.h" 2
# 145 "include/apt32f102_syscon.h"
typedef enum
{
 ENDIS_ISOSC = (CSP_REGISTER_T)(0x01ul),
 ENDIS_IMOSC = (CSP_REGISTER_T)(0x01ul<<1),
 ENDIS_EMOSC = (CSP_REGISTER_T)(0x01ul<<3),
 ENDIS_HFOSC = (CSP_REGISTER_T)(0x01ul<<4),
 ENDIS_IDLE_PCLK = (CSP_REGISTER_T)(0x01ul<<8),
 ENDIS_SYSTICK = (CSP_REGISTER_T)(0x01ul<<11)
}SYSCON_General_CMD_TypeDef;




typedef enum
{
 SYSCLK_IMOSC = (CSP_REGISTER_T)0x0ul,
 SYSCLK_EMOSC = (CSP_REGISTER_T)0x1ul,
 SYSCLK_HFOSC = (CSP_REGISTER_T)0x2ul,
 SYSCLK_ISOSC = (CSP_REGISTER_T)0x4ul

}SystemCLK_TypeDef;



typedef enum
{
 HCLK_DIV_1 = (CSP_REGISTER_T)(0x1ul<<8),
 HCLK_DIV_2 = (CSP_REGISTER_T)(0x2ul<<8),
 HCLK_DIV_3 = (CSP_REGISTER_T)(0x3ul<<8),
 HCLK_DIV_4 = (CSP_REGISTER_T)(0x4ul<<8),
 HCLK_DIV_5 = (CSP_REGISTER_T)(0x5ul<<8),
 HCLK_DIV_6 = (CSP_REGISTER_T)(0x6ul<<8),
 HCLK_DIV_7 = (CSP_REGISTER_T)(0x7ul<<8),
 HCLK_DIV_8 = (CSP_REGISTER_T)(0x8ul<<8),
 HCLK_DIV_12 = (CSP_REGISTER_T)(0x9ul<<8),
 HCLK_DIV_16 = (CSP_REGISTER_T)(0xAul<<8),
 HCLK_DIV_24 = (CSP_REGISTER_T)(0xBul<<8),
 HCLK_DIV_32 = (CSP_REGISTER_T)(0xCul<<8),
 HCLK_DIV_64 = (CSP_REGISTER_T)(0xDul<<8),
 HCLK_DIV_128 = (CSP_REGISTER_T)(0xEul<<8),
 HCLK_DIV_256 = (CSP_REGISTER_T)(0xFul<<8)
}SystemCLK_Div_TypeDef;




typedef enum
{
 PCLK_DIV_1 = (CSP_REGISTER_T)(0x00ul<<8),
 PCLK_DIV_2 = (CSP_REGISTER_T)(0x01ul<<8),
 PCLK_DIV_4 = (CSP_REGISTER_T)(0x02ul<<8),
 PCLK_DIV_8 = (CSP_REGISTER_T)(0x04ul<<8),
 PCLK_DIV_16 = (CSP_REGISTER_T)(0x08ul<<8)
}PCLK_Div_TypeDef;




typedef enum
{
 ENABLE_LVDEN = (CSP_REGISTER_T)0x00,
 DISABLE_LVDEN = (CSP_REGISTER_T)0x0a
}X_LVDEN_TypeDef;




typedef enum
{
 INTDET_LVL_2_1V = (CSP_REGISTER_T)(0X00ul<<8),
 INTDET_LVL_2_4V = (CSP_REGISTER_T)(0X01ul<<8),
 INTDET_LVL_2_7V = (CSP_REGISTER_T)(0X02ul<<8),
 INTDET_LVL_3_0V = (CSP_REGISTER_T)(0X03ul<<8),
 INTDET_LVL_3_3V = (CSP_REGISTER_T)(0X04ul<<8),
 INTDET_LVL_3_6V = (CSP_REGISTER_T)(0X05ul<<8),
 INTDET_LVL_3_9V = (CSP_REGISTER_T)(0X06ul<<8),
}INTDET_LVL_X_TypeDef;




typedef enum
{
 RSTDET_LVL_1_9V = (CSP_REGISTER_T)(0X00ul<<12),
 RSTDET_LVL_2_2V = (CSP_REGISTER_T)(0X01ul<<12),
    RSTDET_LVL_2_5V = (CSP_REGISTER_T)(0X02ul<<12),
 RSTDET_LVL_2_8V = (CSP_REGISTER_T)(0X03ul<<12),
 RSTDET_LVL_3_1V = (CSP_REGISTER_T)(0X04ul<<12),
 RSTDET_LVL_3_4V = (CSP_REGISTER_T)(0X05ul<<12),
 RSTDET_LVL_3_7V = (CSP_REGISTER_T)(0X06ul<<12),
 RSTDET_LVL_4_0V = (CSP_REGISTER_T)(0X07ul<<12)
}RSTDET_LVL_X_TypeDef;




typedef enum
{
 ENABLE_LVD_INT = (CSP_REGISTER_T)(0X01ul<<11),
 DISABLE_LVD_INT = (CSP_REGISTER_T)(0X00ul<<11)
}X_LVD_INT_TypeDef;




typedef enum
{
 EXI_PIN0 = (CSP_REGISTER_T)(0X01ul),
 EXI_PIN1 = (CSP_REGISTER_T)(0X01ul<<1),
 EXI_PIN2 = (CSP_REGISTER_T)(0X01ul<<2),
 EXI_PIN3 = (CSP_REGISTER_T)(0X01ul<<3),
 EXI_PIN4 = (CSP_REGISTER_T)(0X01ul<<4),
 EXI_PIN5 = (CSP_REGISTER_T)(0X01ul<<5),
 EXI_PIN6 = (CSP_REGISTER_T)(0X01ul<<6),
 EXI_PIN7 = (CSP_REGISTER_T)(0X01ul<<7),
 EXI_PIN8 = (CSP_REGISTER_T)(0X01ul<<8),
 EXI_PIN9 = (CSP_REGISTER_T)(0X01ul<<9),
 EXI_PIN10 = (CSP_REGISTER_T)(0X01ul<<10),
 EXI_PIN11 = (CSP_REGISTER_T)(0X01ul<<11),
 EXI_PIN12 = (CSP_REGISTER_T)(0X01ul<<12),
 EXI_PIN13 = (CSP_REGISTER_T)(0X01ul<<13),
 EXI_PIN14 = (CSP_REGISTER_T)(0X01ul<<14),
 EXI_PIN15 = (CSP_REGISTER_T)(0X01ul<<15),
 EXI_PIN16 = (CSP_REGISTER_T)(0X01ul<<16),
 EXI_PIN17 = (CSP_REGISTER_T)(0X01ul<<17),
 EXI_PIN18 = (CSP_REGISTER_T)(0X01ul<<18),
 EXI_PIN19 = (CSP_REGISTER_T)(0X01ul<<19),
}SYSCON_EXIPIN_TypeDef;




typedef enum
{
 _EXIRT = 0,
 _EXIFT = 1,
}EXI_tringer_mode_TypeDef;





typedef enum
{
 IWDT_TIME_125MS = (CSP_REGISTER_T)(0x00ul<<8),
 IWDT_TIME_250MS = (CSP_REGISTER_T)(0x01ul<<8),
 IWDT_TIME_500MS = (CSP_REGISTER_T)(0x02ul<<8),
 IWDT_TIME_1S = (CSP_REGISTER_T)(0x03ul<<8),
 IWDT_TIME_2S = (CSP_REGISTER_T)(0x04ul<<8),
 IWDT_TIME_3S = (CSP_REGISTER_T)(0x05ul<<8),
 IWDT_TIME_4S = (CSP_REGISTER_T)(0x06ul<<8),
 IWDT_TIME_8S = (CSP_REGISTER_T)(0x07ul<<8)
}IWDT_TIME_TypeDef;




typedef enum
{
 IWDT_INTW_DIV_1 = (0x00ul<<2),
 IWDT_INTW_DIV_2 = (0x01ul<<2),
 IWDT_INTW_DIV_3 = (0x02ul<<2),
 IWDT_INTW_DIV_4 = (0x03ul<<2),
 IWDT_INTW_DIV_5 = (0x04ul<<2),
 IWDT_INTW_DIV_6 = (0x05ul<<2),
 IWDT_INTW_DIV_7 = (0x06ul<<2)
}IWDT_TIMEDIV_TypeDef;




typedef enum
{
 IMOSC_SELECTE_5556K = (0x00ul<<0),
 IMOSC_SELECTE_4194K = (0x01ul<<0),
 IMOSC_SELECTE_2097K = (0x02ul<<0),
 IMOSC_SELECTE_131K = (0x03ul<<0)
}IMOSC_SELECTE_TypeDef;




typedef enum
{
 HFOSC_SELECTE_48M = (0x0ul<<4),
 HFOSC_SELECTE_24M = (0x1ul<<4),
 HFOSC_SELECTE_12M = (0x2ul<<4),
 HFOSC_SELECTE_6M = (0x3ul<<4)
}HFOSC_SELECTE_TypeDef;




typedef enum
{
 EM_FLSEL_5ns = (0x0ul<<26),
 EM_FLSEL_10ns = (0x1ul<<26),
 EM_FLSEL_15ns = (0x2ul<<26),
 EM_FLSEL_20ns = (0x3ul<<26)
}EM_Filter_TypeDef;



typedef enum
{
 EM_FLEN_DIS = (0x0ul<<25),
 EM_FLEN_EN = (0x1ul<<25)
}EM_Filter_CMD_TypeDef;



typedef enum
{
 EM_LFSEL_DIS = (0x0ul<<10),
 EM_LFSEL_EN = (0x1ul<<10)
}EM_LFSEL_TypeDef;



typedef enum
{
 EMOSC_24M = 0,
 EMOSC_16M = 1,
 EMOSC_12M = 2,
 EMOSC_8M = 3,
 EMOSC_4M = 4,
 EMOSC_36K = 5,
 IMOSC = 6,
 ISOSC = 7,
 HFOSC_48M = 8,
 HFOSC_24M = 9,
 HFOSC_12M = 10,
 HFOSC_6M = 11
}SystemClk_data_TypeDef;
typedef enum
{
 CLO_PA02 = 0,
 CLO_PA08 = 1,
}CLO_IO_TypeDef;

typedef enum
{
 INTDET_POL_fall = (1<<6),
 INTDET_POL_X_rise = (2<<6),
 INTDET_POL_X_riseORfall = (3<<6),
}INTDET_POL_X_TypeDef;



extern void SYSCON_RST_VALUE(void);
extern void SYSCON_General_CMD(FunctionalStatus NewState, SYSCON_General_CMD_TypeDef ENDIS_X );
extern void EMOSC_OSTR_Config(U16_T EM_CNT, U8_T EM_GM,EM_LFSEL_TypeDef EM_LFSEL_X, EM_Filter_CMD_TypeDef EM_FLEN_X, EM_Filter_TypeDef EM_FLSEL_X);
extern void SystemCLK_HCLKDIV_PCLKDIV_Config(SystemCLK_TypeDef SYSCLK_X , SystemCLK_Div_TypeDef HCLK_DIV_X , PCLK_Div_TypeDef PCLK_DIV_X , SystemClk_data_TypeDef SystemClk_data_x );
extern void SYSCON_WDT_CMD(FunctionalStatus NewState);
extern void SYSCON_IWDCNT_Reload(void);
extern void SYSCON_IWDCNT_Config(IWDT_TIME_TypeDef IWDT_TIME_X , IWDT_TIMEDIV_TypeDef IWDT_INTW_DIV_X );
extern void SYSCON_LVD_Config(X_LVDEN_TypeDef X_LVDEN , INTDET_LVL_X_TypeDef INTDET_LVL_X , RSTDET_LVL_X_TypeDef RSTDET_LVL_X , X_LVD_INT_TypeDef X_LVD_INT , INTDET_POL_X_TypeDef INTDET_POL_X);
extern void EXTI_trigger_CMD(FunctionalStatus NewState , SYSCON_EXIPIN_TypeDef EXIPIN , EXI_tringer_mode_TypeDef EXI_tringer_mode);
extern void EXTI_interrupt_CMD(FunctionalStatus NewState , SYSCON_EXIPIN_TypeDef EXIPIN);
extern void SYSCON_CLO_CONFIG(CLO_IO_TypeDef clo_io);
extern U32_T SYSCON_Read_CINF0(void);
extern U32_T SYSCON_Read_CINF1(void);
extern void SYSCON_INT_Priority(void);
extern void EXI0_Int_Enable(void);
extern void EXI0_Int_Disable(void);
extern void EXI1_Int_Enable(void);
extern void EXI1_Int_Disable(void);
extern void EXI2_Int_Enable(void);
extern void EXI2_Int_Disable(void);
extern void EXI3_Int_Enable(void);
extern void EXI3_Int_Disable(void);
extern void EXI4_Int_Enable(void);
extern void EXI4_Int_Disable(void);
extern void SYSCON_Int_Enable(void);
extern void SYSCON_Int_Disable(void);
extern void PCLK_goto_idle_mode(void);
extern void PCLK_goto_deepsleep_mode(void);
extern void LVD_Int_Enable(void);
extern void LVD_Int_Disable(void);
extern void IWDT_Int_Enable(void);
extern void IWDT_Int_Disable(void);
extern void EXI0_WakeUp_Enable(void);
extern void EXI0_WakeUp_Disable(void);
extern void EXI1_WakeUp_Enable(void);
extern void EXI1_WakeUp_Disable(void);
extern void EXI2_WakeUp_Enable(void);
extern void EXI2_WakeUp_Disable(void);
extern void EXI3_WakeUp_Enable(void);
extern void EXI3_WakeUp_Disable(void);
extern void EXI4_WakeUp_Enable(void);
extern void EXI4_WakeUp_Disable(void);
extern void SYSCON_WakeUp_Enable(void);
extern void SYSCON_WakeUp_Disable(void);
extern void GPIO_EXTI_interrupt(CSP_GPIO_T * GPIOX,U32_T GPIO_IECR_VALUE);
extern void SYSCON_Software_Reset(void);
extern void SYSCON_HFOSC_SELECTE(HFOSC_SELECTE_TypeDef HFOSC_SELECTE_X);
extern void SYSCON_IMOSC_SELECTE(IMOSC_SELECTE_TypeDef IMOSC_SELECTE_X);
# 20 "FWlib/apt32f102_syscon.c" 2
# 30 "FWlib/apt32f102_syscon.c"
void SYSCON_RST_VALUE(void)
{





 SYSCON->RAMCHK=((CSP_REGISTER_T)0x0000ffff);
 SYSCON->EFLCHK=((CSP_REGISTER_T)(0X0<<24)|0xffffff);
 SYSCON->SCLKCR=((CSP_REGISTER_T)0xD22Dul<<16);







 SYSCON->OSTR=((CSP_REGISTER_T)0x70ff3bff);
 SYSCON->LVDCR=((CSP_REGISTER_T)0x0000000a);
# 58 "FWlib/apt32f102_syscon.c"
 SYSCON->EXIRT=((CSP_REGISTER_T)0x00000000);
 SYSCON->EXIFT=((CSP_REGISTER_T)0x00000000);






 SYSCON->IWDCR=((CSP_REGISTER_T)0x0000070C);
 SYSCON->IWDCNT=((CSP_REGISTER_T)0x000003fe);

 SYSCON->EVTRG=((CSP_REGISTER_T)0x00000000);
 SYSCON->EVPS=((CSP_REGISTER_T)0x00000000);
 SYSCON->EVSWF=((CSP_REGISTER_T)0x00000000);
 SYSCON->UREG0=((CSP_REGISTER_T)0x00000000);
 SYSCON->UREG1=((CSP_REGISTER_T)0x00000000);
 SYSCON->UREG2=((CSP_REGISTER_T)0x00000000);
 SYSCON->UREG3=((CSP_REGISTER_T)0x00000000);
}







void EMOSC_OSTR_Config(U16_T EM_CNT, U8_T EM_GM,EM_LFSEL_TypeDef EM_LFSEL_X, EM_Filter_CMD_TypeDef EM_FLEN_X, EM_Filter_TypeDef EM_FLSEL_X)
{
 SYSCON->OSTR=EM_CNT|(EM_GM<<11)|EM_LFSEL_X|EM_FLEN_X|EM_FLSEL_X;
}







void SYSCON_General_CMD(FunctionalStatus NewState, SYSCON_General_CMD_TypeDef ENDIS_X )
{
 if (NewState != DISABLE)
 {
  if(ENDIS_X==ENDIS_EMOSC)
  GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFF00FFF)|0x00044000;
  SYSCON->GCER|=ENDIS_X;
  while(!(SYSCON->GCSR&ENDIS_X));
  switch(ENDIS_X)
  {
   case ENDIS_IMOSC:
    while (!(SYSCON->CKST & ENDIS_IMOSC));
    break;
   case ENDIS_EMOSC:
    while (!(SYSCON->CKST & ENDIS_EMOSC));
    break;
   case ENDIS_ISOSC:
    while (!(SYSCON->CKST & ENDIS_ISOSC));
    break;
   case ENDIS_HFOSC:
    while (!(SYSCON->CKST & ENDIS_HFOSC));
    break;
   case ENDIS_IDLE_PCLK:
    break;
   case ENDIS_SYSTICK:
    break;
  }
 }
 else
 {
  SYSCON->GCDR|=ENDIS_X;
  while(SYSCON->GCSR&ENDIS_X);
  SYSCON->ICR|=ENDIS_X;
 }
}
# 140 "FWlib/apt32f102_syscon.c"
void SystemCLK_HCLKDIV_PCLKDIV_Config(SystemCLK_TypeDef SYSCLK_X , SystemCLK_Div_TypeDef HCLK_DIV_X , PCLK_Div_TypeDef PCLK_DIV_X , SystemClk_data_TypeDef SystemClk_data_x )
{
 if(SystemClk_data_x==HFOSC_48M)
 {
  IFC->CEDR=0X01;
  IFC->MR=0X02|(0X01<<16);
 }
 if((SystemClk_data_x==EMOSC_24M)||(SystemClk_data_x==EMOSC_16M)||(SystemClk_data_x==HFOSC_24M))
 {
  IFC->CEDR=0X01;
  IFC->MR=0X01|(0X01<<16);
 }
 if((SystemClk_data_x==EMOSC_12M)||(SystemClk_data_x==EMOSC_8M)||(SystemClk_data_x==EMOSC_4M)||(SystemClk_data_x==EMOSC_36K)
  ||(SystemClk_data_x==IMOSC)||(SystemClk_data_x==ISOSC)||(SystemClk_data_x==HFOSC_12M)||(SystemClk_data_x==HFOSC_6M))
 {
  IFC->CEDR=0X01;
  IFC->MR=0X00|(0X00<<16);
 }
 SYSCON->SCLKCR=(0xD22Dul<<16) | HCLK_DIV_X| SYSCLK_X;
 while (!(SYSCON->CKST & (1<<8)));
 SYSCON->PCLKCR=(0xC33Cul<<16)|PCLK_DIV_X;
 while(SYSCON->PCLKCR!=PCLK_DIV_X);
}






void SYSCON_IMOSC_SELECTE(IMOSC_SELECTE_TypeDef IMOSC_SELECTE_X)
{
 SYSCON_General_CMD(DISABLE,ENDIS_IMOSC);
 SYSCON->OPT1 = (SYSCON->OPT1 & 0XFFFFFFFC)|IMOSC_SELECTE_X;
 SYSCON_General_CMD(ENABLE,ENDIS_IMOSC);
}






void SYSCON_HFOSC_SELECTE(HFOSC_SELECTE_TypeDef HFOSC_SELECTE_X)
{
 SYSCON_General_CMD(DISABLE,ENDIS_HFOSC);
 SYSCON->OPT1 = (SYSCON->OPT1 & 0XFFFFFFCF)|HFOSC_SELECTE_X;
 SYSCON_General_CMD(ENABLE,ENDIS_HFOSC);
}






void SYSCON_WDT_CMD(FunctionalStatus NewState)
{
 if(NewState != DISABLE)
 {
  SYSCON->IWDEDR=(0x7887ul<<16)|(0x0);
  while(!(SYSCON->IWDCR&(0x01ul<<12)));
 }
 else
 {
  SYSCON->IWDEDR=(0x7887ul<<16)|(0x55aa);
  while(SYSCON->IWDCR&(0x01ul<<12));
 }
}





void SYSCON_IWDCNT_Reload(void)
{
 SYSCON->IWDCNT=(0x5aul<<24);
}
# 223 "FWlib/apt32f102_syscon.c"
void SYSCON_IWDCNT_Config(IWDT_TIME_TypeDef IWDT_TIME_X , IWDT_TIMEDIV_TypeDef IWDT_INTW_DIV_X )
{
 SYSCON->IWDCR=(0x8778ul<<16)|IWDT_TIME_X|IWDT_INTW_DIV_X;
}
# 237 "FWlib/apt32f102_syscon.c"
void SYSCON_LVD_Config(X_LVDEN_TypeDef X_LVDEN , INTDET_LVL_X_TypeDef INTDET_LVL_X , RSTDET_LVL_X_TypeDef RSTDET_LVL_X , X_LVD_INT_TypeDef X_LVD_INT , INTDET_POL_X_TypeDef INTDET_POL_X)
{

 SYSCON->LVDCR=(0xB44Bul<<16)|X_LVDEN|INTDET_LVL_X|RSTDET_LVL_X|X_LVD_INT|INTDET_POL_X;
}





void LVD_Int_Enable(void)
{
 SYSCON->ICR = (0x01ul<<11);
 SYSCON->IMER |= (0x01ul<<11);
}





void LVD_Int_Disable(void)
{
 SYSCON->IMDR |= (0x01ul<<11);
}





void IWDT_Int_Enable(void)
{
 SYSCON->ICR = (0x01ul<<8);
 SYSCON->IMER |= (0x01ul<<8);
}





void IWDT_Int_Disable(void)
{
 SYSCON->IMDR |= (0x01ul<<8);
}
# 292 "FWlib/apt32f102_syscon.c"
U32_T Read_Reset_Status(void)
{
 return (SYSCON->RSR & 0x1ff);
}
# 304 "FWlib/apt32f102_syscon.c"
void EXTI_trigger_CMD(FunctionalStatus NewState , SYSCON_EXIPIN_TypeDef EXIPIN , EXI_tringer_mode_TypeDef EXI_tringer_mode)
{
 switch(EXI_tringer_mode)
 {
  case _EXIRT:
  if(NewState != DISABLE)
  {
   SYSCON->EXIRT |=EXIPIN;
  }
  else
  {
   SYSCON->EXIRT &=~EXIPIN;
  }
  break;
  case _EXIFT:
  if(NewState != DISABLE)
  {
   SYSCON->EXIFT |=EXIPIN;
  }
  else
  {
   SYSCON->EXIFT &=~EXIPIN;
  }
  break;
 }
}
# 338 "FWlib/apt32f102_syscon.c"
void EXTI_interrupt_CMD(FunctionalStatus NewState , SYSCON_EXIPIN_TypeDef EXIPIN)
{
 SYSCON->EXICR = 0X3FFF;
 if(NewState != DISABLE)
 {
  SYSCON->EXIER|=EXIPIN;
  while(!(SYSCON->EXIMR&EXIPIN));
  SYSCON->EXICR |=EXIPIN;
 }
 else
 {
  SYSCON->EXIDR|=EXIPIN;
 }
}





void GPIO_EXTI_interrupt(CSP_GPIO_T * GPIOX,U32_T GPIO_IECR_VALUE)
{
 GPIOX->IECR=GPIO_IECR_VALUE;
}





void PCLK_goto_idle_mode(void)
{
 asm ("doze");
}





void PCLK_goto_deepsleep_mode(void)
{
 SYSCON->WKCR=0X3F<<8;
 asm ("stop");
}





void EXI0_Int_Enable(void)
{
 *(volatile UINT32 *) (0xE000E000 +0x100 ) = (0x01ul<<7);
}






void EXI0_Int_Disable(void)
{
    *(volatile UINT32 *) (0xE000E000 +0x180 ) = (0x01ul<<7);
}






void EXI1_Int_Enable(void)
{
 *(volatile UINT32 *) (0xE000E000 +0x100 ) = (0x01ul<<8);
}






void EXI1_Int_Disable(void)
{
    *(volatile UINT32 *) (0xE000E000 +0x180 ) = (0x01ul<<8);
}






void EXI2_Int_Enable(void)
{
 *(volatile UINT32 *) (0xE000E000 +0x100 ) = (0x01ul<<21);
}






void EXI2_Int_Disable(void)
{
    *(volatile UINT32 *) (0xE000E000 +0x180 ) = (0x01ul<<21);
}






void EXI3_Int_Enable(void)
{
 *(volatile UINT32 *) (0xE000E000 +0x100 ) = (0x01ul<<22);
}






void EXI3_Int_Disable(void)
{
    *(volatile UINT32 *) (0xE000E000 +0x180 ) = (0x01ul<<22);
}






void EXI4_Int_Enable(void)
{
 *(volatile UINT32 *) (0xE000E000 +0x100 ) = (0x01ul<<23);
}






void EXI4_Int_Disable(void)
{
    *(volatile UINT32 *) (0xE000E000 +0x180 ) = (0x01ul<<23);
}





void EXI0_WakeUp_Enable(void)
{
    *(volatile UINT32 *) (0xE000E000 +0x140 ) = (0x01ul<<7);
}






void EXI0_WakeUp_Disable(void)
{
    *(volatile UINT32 *) (0xE000E000 +0x1C0 ) = (0x01ul<<7);
}






void EXI1_WakeUp_Enable(void)
{
    *(volatile UINT32 *) (0xE000E000 +0x140 ) = (0x01ul<<8);
}






void EXI1_WakeUp_Disable(void)
{
    *(volatile UINT32 *) (0xE000E000 +0x1C0 ) = (0x01ul<<8);
}






void EXI2_WakeUp_Enable(void)
{
    *(volatile UINT32 *) (0xE000E000 +0x140 ) = (0x01ul<<21);
}






void EXI2_WakeUp_Disable(void)
{
    *(volatile UINT32 *) (0xE000E000 +0x1C0 ) = (0x01ul<<21);
}






void EXI3_WakeUp_Enable(void)
{
    *(volatile UINT32 *) (0xE000E000 +0x140 ) = (0x01ul<<22);
}






void EXI3_WakeUp_Disable(void)
{
    *(volatile UINT32 *) (0xE000E000 +0x1C0 ) = (0x01ul<<22);
}






void EXI4_WakeUp_Enable(void)
{
    *(volatile UINT32 *) (0xE000E000 +0x140 ) = (0x01ul<<23);
}






void EXI4_WakeUp_Disable(void)
{
    *(volatile UINT32 *) (0xE000E000 +0x1C0 ) = (0x01ul<<23);
}





void SYSCON_Int_Enable(void)
{
    *(volatile UINT32 *) (0xE000E000 +0x100 ) = (0x01ul<<1);
}






void SYSCON_Int_Disable(void)
{
    *(volatile UINT32 *) (0xE000E000 +0x180 ) = (0x01ul<<1);
}





void SYSCON_WakeUp_Enable(void)
{
    *(volatile UINT32 *) (0xE000E000 +0x140 ) = (0x01ul<<1);
}





void SYSCON_CLO_CONFIG(CLO_IO_TypeDef clo_io)
{
 if (clo_io==CLO_PA02)
 {
  GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0X00000700;
 }
 if (clo_io==CLO_PA08)
 {
  GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0) | 0X00000007;
 }

}





void SYSCON_WakeUp_Disable(void)
{
    *(volatile UINT32 *) (0xE000E000 +0x1C0 ) = (0x01ul<<1);
}





U32_T SYSCON_Read_CINF0(void)
{
    U32_T value = 0;
    value=SYSCON->CINF0;
    return value;
}





U32_T SYSCON_Read_CINF1(void)
{
    U32_T value = 0;
    value=SYSCON->CINF1;
    return value;
}





void SYSCON_Software_Reset(void)
{
 SYSCON->IDCCR=(0xE11Eul<<16)|(0X01ul<<7);
}
# 698 "FWlib/apt32f102_syscon.c"
void SYSCON_INT_Priority(void)
{
 *(volatile UINT32 *) (0xE000E000 +0x400 ) = 0X40404040;
 *(volatile UINT32 *) (0xE000E000 +0x404 ) = 0X40404000;
 *(volatile UINT32 *) (0xE000E000 +0x408 ) = 0X40404040;
 *(volatile UINT32 *) (0xE000E000 +0x40C ) = 0X40404040;
 *(volatile UINT32 *) (0xE000E000 +0x410 ) = 0X40404040;
 *(volatile UINT32 *) (0xE000E000 +0x414 ) = 0X40404040;
 *(volatile UINT32 *) (0xE000E000 +0x418 ) = 0X40404040;
 *(volatile UINT32 *) (0xE000E000 +0x41C ) = 0X40404040;
}
